In advanced high density semiconductor manufacturing processes, the number of capacitors and resistors is suggested to be reduced. As such, digital phase-locked loop (DPLL) circuits or all digital phase-locked loop (ADPLL) circuits are employed to replace analog phase-locked loop circuits for suitable applications because analog phase-locked loop circuits often require more capacitors and resistors than DPLL or ADPLL circuits. An ADPLL circuit may include a digital phase detector (also known as a digital phase comparator) to detect phase differences between a digitally controlled oscillator (DCO) signal and a reference clock signal. The digital phase detector generates a control signal to the DCO for adjustment in response to the detected phase differences. As a result, skew between the DCO signal and the reference clock signal can be eliminated in the closed loop.
Some existing ADPLL or DPLL circuits such as a Time-to-Digital Converter (TDC) based DPLL circuit are complicated in architecture and typically consume more power than PLL circuits in order to achieve high accuracy. PLL circuits that employ bang-bang phase detector (BBPD) may be easy to design and is simpler than the TDC based PLL circuits, but unfortunately the associated application is limited due to poor jitter performance of BBPD.